Memory tags in the form of radio frequency identification (RFID) tags are well known in the prior art. RFID tags come in many forms but all comprise an integrated circuit on which, in use, data can be stored and a coil which enables it to be interrogated by a reader that also powers it by means of an inductive (wireless) link. Generally RFID tags are quite large, due to the frequency they operate at (13.56 megahertz) and the size of coil they thus require, and operate over large ranges and have very small storage capacities. Smaller RFID tags have also been developed, operating at various frequencies, but still having small storage capacity. Some RFID tags include read-only memory (ROM) and are written to at the time of manufacture, whilst others have read and write capability.
Memory tags incorporate a number of elements. These include an antenna which couples inductively with an antenna in a tag reader, an RF decoder for decoding radio frequency signals received via the antenna, a processor for processing the received signals and an area of non-volatile memory. It is desirable to maximise the area of a memory tag which can be utilised for the provision of memory as this is its purpose. Additionally, it is desirable to reduce the size of memory tags. The smaller a memory tag is, the more versatile it is.
Memory tags do not comprise an on board power supply. As already noted, they are powered via an inductive link with a memory tag reader that is brought into sufficiently close proximity with the memory tag. Hence, power consumption within the memory tag must also be kept to a minimum.
As noted, one of the elements within a memory tag is a processor. FIG. 1 illustrates the architecture and operation of a basic, general purpose, microprocessor. Microprocessor 100 comprises a bus control unit 102, an arithmetic logic unit 104, a number of registers 106 and an instruction decoder/micro sequencer 108. The instruction decoder/micro sequencer 108 is connected to pass signals to the bus control unit 102, the arithmetic logic unit 104 and the registers 106. The bus control unit 102, the arithmetic logic unit 104, the registers 106 and the instruction decoder/micro sequencer 108 are also connected for the transmission of data between them and also to the exterior of microprocessor 100.
The bus control unit 102 contains a program counter 110 and a read write signal generator 112. The program counter has the ability to increment its value by one when appropriate and to reset to zero when appropriate. The program counter enables the bus control unit 102 to control the period of time over which the bus is controlled for each action that is to be carried out. The read write signal generator 110 is operative to control the read and write lines, which are connected to the bus control unit and an associated memory, in order to inform the memory of whether a value is to be set in the memory or whether a value is to be read out from the memory. The bus control unit also indicates to the memory the address at which the value is to be set within the memory, or the address from which the value is to be read.
The arithmetic logic unit 104 is a module within the micro processor which serves to carry out arithmetical operations when told to do so by the instruction decoder/micro sequencer 108. The arithmetic operations performed by the arithmetic logic unit include addition, subtraction, multiplication and division. The registers 106 are temporary working memory. These are operative to hold, temporarily, data which is being passed to or from the arithmetic logic unit 104.
The instruction decoder/micro sequencer 108 is the control module for the micro processor. It controls each of the other modules within the micro processor in accordance with instructions it receives from memory via the data bus. This module is operative to instruct the appropriate register to latch the value currently on the data bus into that register and to hold it there. It is operative to tell the appropriate register to latch into its storage the value that is currently being output by the arithmetic logic unit 108 and it is operative to tell the program counter 110 in the bus control unit 102 either to latch the value currently on the data bus, to increment its value, or to reset to zero. The instruction decoder/micro sequencer module 108 also operates to tell the arithmetic logic unit 104 which operation should be performed upon data that is passed into it. It also controls the bus control unit 102 to carry out, as the next operation, a write routine or a read routine. This enables the bus control unit to activate the appropriate control lines. Finally, this module is operative to load the next instruction from the data bus.
As the skilled reader will appreciate, the above is a brief overview of a general purpose processor. Such processors can execute any kind of application. However, they have associated with them a number of significant disadvantages. Amongst these are inefficient data movement within the processor, complex instruction decoding and high power consumption.
Memory tags typically operate at a very high data rate, such as 10 mega bits per second (10 Mbps). Typically, general purpose processors are too big for efficient use in memory tags. Their footprint, for example in Silicon, can be larger than the available size of the memory tag in total. This is because of the associated complexity of decoding instructions and/or the requirement to process data at high rates (such as 10 Mbps per second). The size of general purpose processors therefore reduces the area of a memory tag that can be given over to memory and/or requires more power than can be provided to run the entire tag in order to carry out computations.
Accordingly, there is a need for a memory tag in which the area of the tag dedicated to memory is maximised, in which data can be processed at a sufficiently high rate and/or in which power consumption during processing is minimised. There is also a need for a processor, suitable for use in a memory tag, which has a minimal footprint, which can process data at a sufficiently high rate and/or which exhibits a minimal power consumption.
US 2003/0039247 discloses a method and apparatus for general purpose packet reception processing.
As stated above, memory tags are generally implemented using an array of non-volatile memory, for example flash memory.
Flash memory has a number of advantages. In particular, no power supply is required to preserve the contents of the flash memory. This means that flash memory is particularly suited for use in memory tags where there is no on-board power supply.
In general, flash memory comprises an array of memory cells. Data is written serially into the memory cells along the columns and rows of the array. The structure of the array is such that the process of writing data serially to the flash memory is convoluted and different amounts of time are required to write the data into the cells depending on where the data is being written relative to the internal boundaries of the memory cells.
The following are characteristics of all types of flash memory:—
(i) the write time is relatively long compared to other types of memory because a certain amount of time is required to program each memory cell at a particular address row and columns;
(ii) the write time required when writing across a page boundary is generally longer than the time required to write within the page;
(iii) single words cannot be erased within the flash memory, only whole pages can be erased and this page erase process takes a long time relative to the write process;
(iv) after a relatively low number of page erases have taken place (approximately 1000 erases), a page becomes physically damaged and unusable.
Conventional systems for writing to flash memory generally comprise a volatile memory buffer which stores data being written to the flash memory before the data is actually written. The buffer allows the integrity of data to be checked before it is written to the flash memory.
If there was no buffer and data was written directly into the flash memory and then its integrity checked and an error detected, a entire page would have to be erased and rewritten (following retransmission of a data packet).
As discussed above, it desirable to reduce the size of memory tags. The smaller a memory tag is, the more versatile it is. In addition, there is a need to reduce power consumption in the memory tag. Memory buffers are large relative to the size of the memory tag and consume additional power. Therefore, it is advantageous to avoid using memory buffers in memory tags to store incoming data before it is written.
Incoming data therefore has to be written into the memory as soon as it arrives. However, in conventional data transmission formats, the checksum for verifying the integrity of the data arrives at the end of the data payload. It is therefore not possible to check the data integrity before it is written.
Accordingly, there is a need for an apparatus and method for writing data into a memory tag which ensures that received data can be error checked before it is written into the flash memory of the memory tag.